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// Analysis
CPU-to-GPU Cache Side-Channel Exposes Apple AI
Published: Tue, 11 Aug 2026 • By Theo Solander
Attacks
New research shows an unprivileged CPU process on Apple Silicon can spy on GPU workloads by watching footprints in the shared system-level cache. The team builds Prime+Probe-style channels that hit 400 Kbps and extracts sensitive AI details, including Large Language Model prompts and Graph Neural Network edges.
Unified memory on Apple Silicon makes CPU and GPU cooperation feel elegant. It also hands attackers a shared plank to tiptoe across. This work shows a CPU process, running without special privileges, can read the telltale footprints that GPU kernels leave in the system-level cache (SLC) and reconstruct what those kernels are doing at set granularity.
We've been here before, in spirit. Every time we combine domains on a shared resource, the walls grow thin. Think of it as eavesdropping through a vent between rooms: you do not need to go next door if you can hear the patterns in the airflow. The novelty here is precision. Earlier integrated-platform attacks either measured coarse cache occupancy or required living on the GPU. This one watches from the CPU with a fine-grained, Prime+Probe cadence.
How the leak works
The authors reverse-engineer the Apple M1 SLC. They recover a 12-bit hashed set index across 4,096 sets, 16-way associative, and map how private CPU caches and GPU caches interact with the SLC. Crucially, GPU memory accesses leave observable set-level footprints in the SLC that the CPU can see.
Building eviction sets is hard when set mapping is hashed and physical addresses are hidden by macOS. The trick is a collision-profile clustering method: group virtual addresses by how often they evict a primed set after controlled GPU fills. With stable groups, they run two priming strategies. CPrime primes entirely from the CPU, using a two-stage path through L2 to ensure SLC fills. GPrime primes from the GPU itself, using write and read kernels to invalidate CPU copies and populate the SLC faster. Probing is always CPU-side (CProbe), timing SLC hits and misses to infer which sets the GPU touched.
The covert channel is not a lab curiosity. CPrime+CProbe hits 62.5 Kbps; GPrime+CProbe pushes throughput to about 400 Kbps, roughly a 6.4x speedup. With that signal, they recover structure from Graph Neural Network (GNN) inference, reconstructing graph edges with over 90% accuracy across five datasets. They also target Large Language Models (LLMs), recovering input keywords with up to 94.8% accuracy and model responses with up to 88.9% accuracy on TinyLlama and GPT-2 Medium. Noise is handled with differential tracing, multi-run averaging, and aggregating related cache sets into supersets.
The work is specific to Apple’s SLC behaviour and unified memory, but the pattern is broader: heterogeneous System-on-Chips make new side-channel perimeters wherever domains share last-level caches. Later Apple parts may tweak GPU caching, which could shift the ground. For now, this is a crisp reminder that performance features often hum the same old tune as leakage channels, just in a fresh key.
Additional analysis of the original ArXiv paper
📋Original Paper Title and Abstract
SLAC: Access-Driven CPU-to-GPU Side-channel Attacks via System-Level Cache on Apple Silicon
Authors: Tianhong Xu, Saion K. Roy, Ruyi Ding, Aidong Adam Ding, and Yunsi Fei
Modern heterogeneous System-on-Chip designs integrate CPU cores and a GPU that share a last-level cache (LLC) or system-level cache (SLC). This sharing exposes a new cross-domain attack surface, and existing attacks on integrated platforms either exploit coarse-grained cache-occupancy contention or require the adversary to co-reside on the GPU with the victim to obtain accurate timing measurements. In this work, we target Apple Silicon heterogeneous SoCs and discover that GPU memory accesses leave set-level footprints in the shared SLC, observable to an unprivileged CPU process. This keen observation enables the first fine-grained, access-driven, Prime+Probe-style CPU-to-GPU cache side-channel attacks against GPU workloads. We first reverse-engineer the Apple M1 SLC set-indexing functions and the interactions between local private caches and the SLC. Building on these findings, we construct the CPrime+CProbe SLC side-channel technique, which monitors GPU victim activity from the CPU at cache-set granularity. We then introduce an accelerated variant, GPrime+CProbe, in which an adversary leverages the GPU for faster SLC priming, yielding a 6.4x increase in the covert-channel throughput. Lastly, we demonstrate two end-to-end privacy attacks using the new side-channels: a graph-edge reconstruction attack on Graph Neural Networks (GNNs) that achieves 90% edge accuracy across five datasets, and an LLM privacy attack that recovers input keywords with up to 94.8% accuracy and model responses with up to 88.9% accuracy across TinyLlama and GPT-2 Medium models. Our results reveal a new class of microarchitectural vulnerabilities in Apple Silicon and call for secure system cache designs for heterogeneous SoCs.
🔍ShortSpan Analysis of the Paper
Problem
The paper investigates whether an unprivileged CPU process on Apple Silicon can observe and exploit GPU memory accesses through the shared system-level cache (SLC). This matters because modern SoCs often run privacy-sensitive GPU workloads such as machine-learning inference, and cross-domain microarchitectural leakage can expose inputs, outputs or model structure without GPU residency or special privileges.
Approach
The authors reverse-engineer the Apple M1 SLC to recover its set-indexing and replacement behaviour, then develop two Prime+Probe-style CPU-to-GPU side channels. They characterise SLC inclusiveness: the SLC is exclusive relative to CPU private caches but non-inclusive non-exclusive relative to GPU caches, enabling GPU accesses to leave observable SLC footprints. To build eviction sets despite a fully hashed 12-bit set index, they introduce a collision-profile clustering method that groups addresses by the pattern of evictions observed after controlled GPU fills. Two priming strategies are implemented: CPrime primes the SLC entirely from the CPU using a two-stage L2 eviction process, and GPrime primes from the GPU using write and read kernels to invalidate CPU copies and populate the SLC. Probing is always done on the CPU (CProbe) to measure SLC hits and misses. The authors evaluate covert-channel throughput and mount two end-to-end privacy attacks: GNN graph-edge reconstruction and LLM input/output recovery, using noise-reduction techniques such as differential tracing, multi-run averaging and cache-set aggregation (supersets).
Key Findings
The SLC on Apple M1 uses a 12-bit hashed set-index mapping to 4,096 sets; associativity is 16 and an attacker-constructed SLC eviction set contains 65,536 cache-line addresses.
GPU memory accesses produce set-level footprints in the SLC that are observable by an unprivileged CPU, enabling the first fine-grained access-driven CPU-to-GPU Prime+Probe attack on Apple Silicon.
CPrime+CProbe (CPU-only priming) achieves a covert channel throughput of 62.5 Kbps; GPrime+CProbe (GPU-assisted priming) speeds priming by about 6.4 times and achieves 400 Kbps covert-channel throughput.
The GNN edge-recovery attack reconstructs graph edges with over 90% accuracy across five benchmark datasets when using these side channels.
The LLM attacks recover input keywords with up to 94.8% accuracy and recover output tokens with up to 88.9% accuracy on TinyLlama and GPT-2 Medium, using superset aggregation and language-model-guided disambiguation.
Limitations
The attacks rely on platform-specific SLC behaviour and on Apple’s unified memory and cache inclusiveness patterns; macOS does not expose physical addresses so eviction-set construction required extensive profiling. CPrime is slower and noisier, needing many averaged runs or aggregation to be reliable; GPrime requires the attacker to execute GPU kernels and to manage cache-coherence complications (GPU write followed by read). Results are demonstrated on M1 and expected to generalise to similar M-series SoCs with calibration; newer designs such as M3 introduce dynamic GPU caching that may alter interactions. Background system activity, page remapping and the need to control page-offset bits impose practical constraints on priming stability and run-time noise.
Implications
An attacker co-resident as an unprivileged CPU process could monitor GPU workloads and extract sensitive information without GPU residency. Practical offensive actions include constructing high-throughput covert channels for data exfiltration, reconstructing graph topology from GNN inference, and recovering LLM prompts and generated tokens. The demonstrated throughputs and accuracies show these attacks are feasible against deployed local AI workloads on Apple Silicon, posing risks to privacy and model confidentiality.
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